1. Field of the Invention
The present invention relates to an output circuit and, more particularly, to an output circuit that can prevent consumption of internal current and introduction of a signal from the outside through a DQ terminal, in such a manner that in a normal operating mode, a first external power is supplied to be used as a second external power, and in a deep power down mode, the supply of the power is shut off and an output driver is made to have a HIGH impedance state, by means of a power bar signal that is applied as a LOW state in the normal operating mode and applied as a HIGH state in the deep power down mode.
2. Discussion of Related Art
As one method for minimizing current consumption in a semiconductor device, a deep power down mode is employed. The deep power down mode is one for shutting off all the internal power to eliminate current flowing therein in order to reduce current consumption. In particular, a semiconductor device such as a pseudo SRAM has both the internal power and the external power used in the output circuit, etc. The conventional output circuit will now be described with reference to FIG. 1.
FIG. 1 is a circuit diagram illustrating the output circuit that is applicable to the semiconductor device such as the conventional pseudo SRAM.
A first inverter I11 inverts a global input/output signal (GIO) and a second inverter I12 inverts an output enable signal (OE). A NOR gate 11 performs a NOR operation for the output signal of the first inverter I11 and the output signal of the second inverter I12 to control the potential of a first node Q11. A first level shifter 12 outputs the potential of an external power (Vextq) or a ground potential depending on the level of the output signal of the NOR gate 11. A fourth inverter I14 inverts the output of the first level shifter 12. A seventh PMOS transistor P17 connected between the external power (Vextq) and a DQ terminal DQ is driven by the output signal of the fourth inverter I14.
A NAND gate 13 performs a NAND operation for the output signal of the first inverter I11 and the output enable signal (OE) to control the potential of a fifth node Q15. A second level shifter 14 outputs the potential of the external power (Vextq) or the ground potential depending on the level of the output signal of the NAND gate 13. A sixth inverter I16 inverts the output of the second level shifter 14. A seventh NMOS transistor N17 connected between the DQ terminal DQ and the ground terminal Vss is driven by the output signal of the sixth inverter I16.
The conventional output circuit constructed above is enabled to output the global input/output signal (GIO) to the DQ terminal DQ if the output enable signal (OE) is applied as a HIGH state. The operation of the conventional output circuit when the global input/output signal (GIO) is applied as the HIGH state may be described as follows:
The first inverter I11 inverts the global input/output signal (GIO) inputted as the HIGH state to output a signal of the LOW state. The second inverter I12 inverts the output enable signal (OE) inputted as the HIGH state to output a signal of the LOW state. The NOR gate 11 uses the output signal of the first inverter I11 that is the LOW state and the output signal of the second inverter I12 that is the LOW state to output a signal of the HIGH state. The first level shifter 12 outputs a signal of the HIGH state, i.e., a signal keeping the potential of the external power (Vextq), depending on the output signal of the NOR gate 11 that is the HIGH state. The output signal of the first level shifter 12 that is the HIGH state is inverted to the LOW state through the fourth inverter I14, so that the fourth node Q14 keeps the LOW state.
Meanwhile, the NAND gate 13 performs a NAND operation for the output signal of the first inverter I11 that keeps a LOW state and the output enable signal (OE) inputted as a HIGH state to output a signal of a HIGH state. The second level shifter 14 outputs a signal of the HIGH state, i.e., a signal keeping the potential of the external power (Vextq), depending on the output signal of the NAND gate 13 that keeps the HIGH state. The output signal of the second level shifter 14 that is the HIGH state is inverted to the LOW state through the sixth inverter I16, so that the eighth node Q18 keeps the LOW state.
Therefore, the seventh PMOS transistor P17 is turned on by the potential of the fourth node Q14 that keeps the LOW state. The seventh NMOS transistor N17 is turned off by the potential of the eighth node Q18 that keeps the LOW state. The external power (Vextq) is thus outputted to the DQ terminal DQ.
Since the conventional output circuit operated and constructed as above uses the external power intact, however, a large amount of current is consumed although the internal power is shut off in the deep power down mode. Specially, the first and second level shifters output the external power depending on the internal power. If the internal power is shut off, the first and second level shifters become floated. In this case, since current flows from the external power to the ground terminal, current is consumed. For this reason, it does not make effective use of the characteristic of the deep power down mode. Furthermore, if the internal power is shut off, the seventh PMOS transistor and the seventh NMOS transistor do not operate. As the signal may be introduced from the outside to the inside through the DQ terminal, however, current is internally consumed.